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Signal Name
-HDMARDY
(True IDE Mode – In Ultra
DMA Protocol DMA
Read)
Dir.
Pin
Description
In True IDE Mode when Ultra DMA mode DMA Read is active,
this signal is asserted by the host to indicate that the host is
read
to receive Ultra DMA data-in bursts. The host may negate
-HDMARDY to pause an Ultra DMA transfer.
In True IDE Mode when Ultra DMA mode DMA Write is active,
HSTROBE
(True IDE Mode – In Ultra
DMA Protocol DMA
Write)
– CD1, – CD2
(PC Card Memory Mode)
this signal is the data out strobe generated by the host. Both
the
rising and falling edge of HSTROBE cause data to be latched by
the device. The host may stop generating HSTROBE edges to
pause an Ultra DMA data-out burst.
These Card Detect pins are connected to ground on the
CompactFlash Storage Card. They are used by the
host to determine that the CompactFlash Storage Card or is fully
– CD1, – CD2
(PC Card I/O Mode)
– CD1, – CD2
(True IDE Mode)
O
26, 25
inserted into its socket.
This signal is the same for all modes.
This signal is the same for all modes.
These input signals are used both to select the card and to
indicate to the card whether a byte or a word operation is being
performed. – CE2 always accesses the odd byte of the word.
– CE1, – CE2
(PC Card Memory Mode)
-CE1 accesses the even byte or the Odd byte of the word
depending on A0 and – CE2. A multiplexing scheme based on
A0,
-CE1, -CE2 allows 8 bit hosts to access all data on D0-D7. See
– CE1, – CE2
(PC Card I/O Mode)
– CS0, – CS1
(True IDE Mode)
– CSEL
(PC Card Memory Mode)
I
7, 32
Table 32 , Table 40 , Table 41Table 42 , and Table 43 .
This signal is the same as the PC Card Memory Mode signal.
In the True IDE Mode, -CS0 is the chip select for the task file
registers while – CS1 is used to select the Alternate Status
Register and the Device Control Register.
While – DMACK is asserted, -CS0 and – CS1 shall be held
negated and the width of the transfers shall be 16 bits.
This signal is not used for this mode, but should be connected
by
the host to PC Card A25 or grounded by the host.
– CSEL
(PC Card I/O Mode)
I
39
This signal is not used for this mode, but should be connected
by
the host to PC Card A25 or grounded by the host.
This internally pulled up signal is used to configure this device
as
– CSEL
(True IDE Mode)
– IOWR
(PC Card Memory Mode)
– IOWR
(PC Card I/O Mode)
a Master or a Slave when configured in the True IDE Mode.
When this pin is grounded, this device is configured as a
Master.
When the pin is open, this device is configured as a Slave.
This signal is not used in this mode.
The I/O Write strobe pulse is used to clock I/O data on the Card
Data bus into the CompactFlash Storage Card controller registers
when the CompactFlash Storage Card is configured to use the I/O
interface.
The clocking shall occur on the negative to positive edge of the
-IOWR
(True IDE Mode – Except
Ultra DMA Protocol
Active)
STOP
(True IDE Mode – Ultra
DMA Protocol Active)
– OE
I
35
signal (trailing edge).
In True IDE Mode, while Ultra DMA mode protocol is not active,
this signal has the same function as in PC Card I/O Mode.
When Ultra DMA mode protocol is supported, this signal must be
negated before entering Ultra DMA mode protocol.
In True IDE Mode, while Ultra DMA mode protocol is active, the
assertion of this signal causes the termination of the Ultra DMA
burst.
This is an Output Enable strobe generated by the host interface.
It is used to read data from the CompactFlash Storage
(PC Card Memory Mode)
– OE
(PC Card I/O Mode)
I
9
in Memory Mode and to read the CIS and
configuration registers.
In PC Card I/O Mode, this signal is used to read the CIS and
configuration registers.
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.20
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-320_data_sheet_CF-HxBO_Rev120.doc
Page 14 of 101
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